This invention relates to the field of computer busses, and more specifically to a method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit.
Computer systems and similar electronic systems and devices are being continually required to perform more operations at faster speeds with more reliability and less power consumption. The density or number of components or elements on a chip or circuit board are being driven up while packaging size and manufacturing costs are being driven down. This presents a challenge to designers to efficiently design systems and chips that optimally utilize the available real estate on a chip or printed circuit board. Additionally, components that need to communicate with one another are desirably located near one another to improve operational efficiency, reduce power consumption and reduce metallization for interconnectons and buses. For those components that because of other constraints must be placed at other locations, the challenge is to provide efficient interconnections for accessing these components.
Thus, there is a need for a method and apparatus for accessing different elements or components that are distributed across a large integrated circuit or distributed in different locations in a system.
The present invention provides a method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit.
One aspect of the present invention provides a method for accessing memory-mapped registers that are distributed across a first integrated circuit, the first integrated circuit including a plurality of logic subset modules, wherein each of the plurality of logic subset modules includes one or more memory-mapped registers. This method includes receiving a memory-mapped register access request into the first integrated circuit, serially transmitting, through each of the plurality of logic subset modules, a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, and within the first logic subset module, accessing the memory-mapped register associated with the first logic subset module.
Another aspect of the present invention provides an MMR circuit for accessing memory-mapped registers that are distributed across a first integrated circuit chip, the first integrated circuit chip including a plurality of logic subset modules, the MMR circuit including a first receiver operable to receive a memory-mapped register access request into the first integrated circuit, an MMR control block within each one of the plurality of logic subset modules, and a ring controller having a serial bus connected through each of the plurality of MMR control blocks, the ring controller coupled to the first receiver and operable to generate a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, wherein based on the address specification, the MMR control block within the first logic subset module, accesses the memory-mapped register associated with the first logic subset module.
Yet another aspect of the present invention provides a multiprocessor system having one of the MMR circuit embodiments described above. This system includes a plurality of integrated circuits including the first integrated circuit, one or more processors operably coupled to each one of the plurality of integrated circuits, a memory operably coupled to each one of the plurality of integrated circuits, and a network operably coupled to each one of the plurality of integrated circuits.
Still another aspect of the present invention provides computer system including one or more processor chips, an integrated circuit operably coupled to the one or more processor chips, the integrated circuit including a plurality of memory-mapped registers that are distributed across the integrated circuit, and means in the integrated circuit for accessing the memory-mapped registers.